`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   18:59:15 01/03/2021
// Design Name:   memory_wrap
// Module Name:   D:/_FPGA/ARC_2020/Lab4_Cache/sword4-test-bench/test/test_mem_cache.v
// Project Name:  sword4-test-bench
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: memory_wrap
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module test_mem_cache;

	// Inputs
	reg clk;
	reg rst;
	reg [31:0] cache_req_addr;
	reg [31:0] cache_req_data;
	reg cache_req_wen;
	reg cache_req_valid;

	// Outputs
	wire [31:0] cache_resp_data;
	wire cache_resp_stall;

	// Instantiate the Unit Under Test (UUT)
	imemory_wrap uut (
		.clk(clk), 
		.rst(rst), 
		.cache_req_addr(cache_req_addr), 
		.cache_req_data(cache_req_data), 
		.cache_req_wen(cache_req_wen), 
		.cache_req_valid(cache_req_valid), 
		.cache_resp_data(cache_resp_data), 
		.cache_resp_stall(cache_resp_stall)
	);
	
	always begin
		#10 clk = ~clk;
	end 

	initial begin
		// Initialize Inputs
		clk = 0;
		rst = 1;
		cache_req_addr = 0;
		cache_req_data = 0;
		cache_req_wen = 0;
		cache_req_valid = 0;

		#40 rst = 0;
		#40;
		cache_req_addr = 0;
		cache_req_data = 32'h0;
		cache_req_wen = 0;
		cache_req_valid = 1;
		
		#260;
		cache_req_addr = 0;
		cache_req_data = 0;
		cache_req_wen = 0;
		cache_req_valid = 0;
		
		
		#60;
		cache_req_addr = 0;
		cache_req_data = 32'h11111111;
		cache_req_wen = 1;
		cache_req_valid = 1;
		
		#60;
		cache_req_addr = 0;
		cache_req_data = 0;
		cache_req_wen = 0;
		cache_req_valid = 0;
		
		#60;
		cache_req_addr = 0;
		cache_req_data = 32'h0;
		cache_req_wen = 0;
		cache_req_valid = 1;
		
		#60;
		cache_req_addr = 0;
		cache_req_data = 0;
		cache_req_wen = 0;
		cache_req_valid = 0;
		
		#60;
		cache_req_addr = 0;
		cache_req_data = 32'h22222222;
		cache_req_wen = 1;
		cache_req_valid = 1;
		
		#60;
		cache_req_addr = 0;
		cache_req_data = 0;
		cache_req_wen = 0;
		cache_req_valid = 0;
		
		#60;
		cache_req_addr = 0;
		cache_req_data = 32'h0;
		cache_req_wen = 0;
		cache_req_valid = 1;
		
		#60;
		cache_req_addr = 0;
		cache_req_data = 0;
		cache_req_wen = 0;
		cache_req_valid = 0;
		
		#60;
		cache_req_addr = 512;
		cache_req_data = 32'h33333333;
		cache_req_wen = 1;
		cache_req_valid = 1;
		
		#360;
		cache_req_addr = 0;
		cache_req_data = 0;
		cache_req_wen = 0;
		cache_req_valid = 0;
		
		#60;
		cache_req_addr = 0;
		cache_req_data = 32'h0;
		cache_req_wen = 0;
		cache_req_valid = 1;
		

	end
      
endmodule

